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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14513B BCD-To-Seven Segment Latch/Decoder/Driver
CMOS MSI (Low-Power Complementary MOS)
The MC14513B BCD-to-seven segment latch/decoder/driver is constructed with complementary MOS (CMOS) enhancement mode devices and NPN bipolar output drivers in a single monolithic structure. The circuit provides the functions of a 4-bit storage latch, an 8421 BCD-to-seven segment decoder, and has output drive capability. Lamp test (LT), blanking (BI), and latch enable (LE) inputs are used to test the display, to turn-off or pulse modulate the brightness of the display, and to store a BCD code, respectively. The Ripple Blanking Input (RBI) and Ripple Blanking Output (RBO) can be used to suppress either leading or trailing zeroes. It can be used with seven-segment light emitting diodes (LED), incandescent, fluorescent, gas discharge, or liquid crystal readouts either directly or indirectly. Applications include instrument (e.g., counter, DVM, etc.) display driver, computer/calculator display driver, cockpit display driver, and various clock, watch, and timer uses. * * * * * * * * * * * Low Logic Circuit Power Dissipation High-current Sourcing Outputs (Up to 25 mA) Latch Storage of Binary Input Blanking Input Lamp Test Provision Readout Blanking on all Illegal Input Combinations Lamp Intensity Modulation Capability Time Share (Multiplexing) Capability Adds Ripple Blanking In, Ripple Blanking Out to MC14511B Supply Voltage Range = 3.0 V to 18 V Capable of Driving Two Low-Power TTL Loads, One Low-power Schottky TTL Load to Two HTL Loads Over the Rated Temperature Range.
L SUFFIX CERAMIC CASE 726 P SUFFIX PLASTIC CASE 707
ORDERING INFORMATION
MC14XXXBCP MC14XXXBCL Plastic Ceramic
TA = - 55 to 125C for all packages.
PIN ASSIGNMENT
B C LT BI LE D A RBI VSS 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 VDD f g a b c d e RBO e d f a g b c
DISPLAY
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MAXIMUM RATINGS* (Voltages Referenced to VSS)
Rating Symbol VDD Vin I TA PD Tstg IOHmax POHmax DC Supply Voltage Value Unit V V mA C mW - 0.5 to + 18 Input Voltage, All Inputs DC Current Drain per Input Pin Operating Temperature Range Power Dissipation, per Package Storage Temperature Range Maximum Continuous Output Drive Current (Source) per Output Maximum Continuous Output Power (Source) per Output - 0.5 to VDD + 0.5 10 - 55 to + 125 500 - 65 to + 150 25 50
0
1
2
3
4
5
6
7
8
9
TRUTH TABLE
Inputs RBI LE BI LT X X 1 0 X X X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 X 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Outputs D C B A RBO a b c d e f g Display XXXX XXXX 0000 0000 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 + + 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1111111 0000000 0000000 1111110 0 1 1 0 1 0 1 1 1 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 0 0 0 0 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 0 0 1 1 0 1 1 0 1 1 0 0 0 0 0 0 * 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 0 0 0 0 0 0 0 1 1 1 1 1 0 1 1 0 0 0 0 0 0 8 Blank Blank 0 1 2 3 4 5 6 7 8 9 Blank Blank Blank Blank Blank Blank *
_C
mA mW
POHmax = IOH (VDD - VOH) * Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: - 12 mW/_C From 100_C To 125_C
REV 3 1/94
XXXX
X = Don't Care RBO = RBI (D C B A), indicated by other rows of table *Depends upon the BCD code previously applied when LE = 0
(c)MC14513B 1995 Motorola, Inc. 376
MOTOROLA CMOS LOGIC DATA
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Symbol VOL VDD Vdc 5.0 10 15 VOH 5.0 10 15 5.0 10 15 VOH 5.0 10 15 5.0 10 15 VIH 5.0 10 15 5.0 Min -- -- -- 4.1 9.1 14.1 -- -- -- 4.95 9.95 14.95 -- -- -- 3.5 7.0 11 4.1 -- 3.9 -- 3.4 -- 9.1 -- 9.0 -- 8.6 -- 14.1 -- 14 -- 13.6 -- - 55_C 25_C 125_C Max Min -- -- -- 4.1 9.1 14.1 -- -- -- 4.95 9.95 14.95 -- -- -- 3.5 7.0 11 4.1 -- 3.9 -- 3.4 -- 9.1 -- 9.0 -- 8.6 -- 14.1 -- 14 -- 13.6 -- Typ # 0 0 0 5.0 10 15 0 0 0 5.0 10 15 2.25 4.50 6.75 2.75 5.50 8.25 4.57 4.24 4.12 3.94 3.70 3.54 9.58 9.26 9.17 9.04 8.90 8.75 14.59 14.27 14.18 14.07 13.95 13.80 Max Min -- -- -- 4.1 9.1 14.1 -- -- -- 4.95 9.95 14.95 -- -- -- 3.5 7.0 11 4.1 -- 3.5 -- 3.0 -- 9.1 -- 8.6 -- 8.2 -- 14.1 -- 13.6 -- 13.2 -- Max Unit Vdc Output Voltage -- Segment Outputs "0" Level Vin = VDD or 0 "1" Level Vin = 0 or VDD Output Voltage -- RBO Output "0" Level Vin = VDD or 0 "1" Level Vin = 0 or VDD Input Voltage # "0" Level (VO = 3.8 or 0.5 Vdc) (VO = 8.8 or 1.0 Vdc) (VO = 13.8 or 1.5 Vdc) (VO = 0.5 or 3.8 Vdc) "1" Level (VO = 1.0 or 8.8 Vdc) (VO = 1.5 or 13.8 Vdc) Output Drive Voltage -- Segments (IOH = 0 mA) Source (IOH = 5.0 mA) (IOH = 10 mA) (IOH = 15 mA) (IOH = 20 mA) (IOH = 25 mA) (IOH = 0 mA) (IOH = 5.0 mA) (IOH = 10 mA) (IOH = 15 mA) (IOH = 20 mA) (IOH = 25 mA) (IOH = 0 mA) (IOH = 5.0 mA) (IOH = 10 mA) (IOH = 15 mA) (IOH = 20 mA) (IOH = 25 mA) VIL 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Vdc Vdc VOL 0.05 0.05 0.05 -- -- -- 0.05 0.05 0.05 -- -- -- 0.05 0.05 0.05 -- -- -- Vdc 0.05 0.05 0.05 -- -- -- 0.05 0.05 0.05 -- -- -- 0.05 0.05 0.05 -- -- -- Vdc Vdc Vdc VOH Vdc 10 15 Vdc (continued) This device contains protection circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. A destructive high current mode may occur if Vin and Vout is not constrained to the range VSS (Vin or Vout) VDD. Due to the sourcing capability of this circuit, damage can occur to the device if VDD is applied, and the outputs are shorted to VSS and are at a logical 1 (See Maximum Ratings). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD).
MOTOROLA CMOS LOGIC DATA
MC14513B 377
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ELECTRICAL CHARACTERISTICS -- continued (Voltages Referenced to VSS)
Characteristic Symbol IOH VDD Vdc 5.0 10 15 IOL 5.0 10 15 5.0 10 15 Iin Cin IDD 15 -- 5.0 10 15 5.0 10 15 - 55_C Min Max -- -- -- -- -- -- -- -- -- 0.1 -- 5.0 10 20 Min 25_C 125_C Typ # Max -- -- -- -- -- -- -- -- -- 0.1 7.5 5.0 10 20 Min Max -- -- -- -- -- -- -- -- -- 1.0 -- 150 300 600 Adc pF Adc mAdc Unit Output Drive Current -- RBO Output (VOH = 2.5 V) Source (VOH = 9.5 V) (VOH = 13.5 V) (VOL = 0.4 V) (VOL = 0.5 V) (VOL = 1.5 V) Sink mAdc - 0.40 - 0.21 - 0.81 0.18 0.47 1.80 0.64 1.6 4.2 -- -- -- -- -- - 0.32 - 0.17 - 0.66 0.15 0.38 1.50 0.51 1.3 3.4 -- -- -- -- -- - 0.64 - 0.34 - 1.30 0.29 0.75 2.90 0.88 2.25 8.8 0.00001 5.0 0.005 0.010 0.015 - 0.22 - 0.12 - 0.46 0.10 0.26 1.0 0.36 0.9 2.4 -- -- -- -- -- Output Drive Current -- Segments (VOL = 0.4 V) Sink (VOL = 0.5 V) (VOL = 1.5 V) Input Current Input Capacitance Quiescent Current (Per Package) Vin = 0 or VDD, Iout = 0 A Total Supply Current** (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) IOL mAdc IT IT = (1.9 A/kHz) f + IDD IT = (3.8 A/kHz) f + IDD IT = (5.7 A/kHz) f + IDD Adc #Noise immunity specified for worst-case input combination. Noise Margin for both "1" and "0" level = 1.0 Vdc min @ VDD = 5.0 Vdc 2.0 Vdc min @ VDD = 10 Vdc 2.5 Vdc min @ VDD = 15 Vdc ** The formulas given are for the typical characteristics only at 25_C. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + 3.5 x 10-3 (CL - 50) VDDf where: IT is in A (per package), CL in pF, VDD in Vdc, and f in kHz is input frequency. Input LE and RBI low, and Inputs D, BI and LT high. f in respect to a system clock. All outputs connected to respective CL loads. 20 ns A, B, AND C 90% 50% 1 2f 20 ns VDD 10% VSS VOH VOL 50% DUTY CYCLE ANY OUTPUT 50%
Figure 1. Dynamic Power Dissipation Signal Waveforms
MC14513B 378
MOTOROLA CMOS LOGIC DATA
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SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Symbol tTLH VDD Vdc 5.0 10 15 Output Rise Time -- RBO Output tTLH 5.0 10 15 Output Fall Time -- Segment Outputs* tTHL = (1.5 ns/pF) CL + 50 ns tTHL = (0.75 ns/pF) CL + 37.5 ns tTHL = (0.55 ns/pF) CL + 37.5 ns Output Fall Time -- RBO Outputs tTHL = (3.25 ns/pF) CL + 107.5 ns tTHL = (1.35 ns/pF) CL + 67.5 ns tTHL = (0.95 ns/pF) CL + 62.5 ns Propagation Delay Time -- A, B, C, D Inputs* tPLH = (0.40 ns/pF) CL + 620 ns tPLH = (0.25 ns/pF) CL + 237.5 ns tPLH = (0.20 ns/pF) CL + 165 ns tPHL = (1.3 ns/pF) CL + 655 ns tPHL = (0.60 ns/pF) CL + 260 ns tPHL = (0.35 ns/pF) CL + 182.5 ns Propagation Delay Time -- RBI and BI Inputs* tPLH = (1.05 ns/pF) CL + 547.5 ns tPLH = (0.45 ns/pF) CL + 177.5 ns tPLH = (0.30 ns/pF) CL + 135 ns tPHL = (0.85 ns/pF) CL + 442.5 ns tPHL = (0.45 ns/pF) CL + 177.5 ns tPHL = (0.35 ns/pF) CL + 142.5 ns Propagation Delay Time -- LT Input* tPLH = (0.45 ns/pF) CL + 290.5 ns tPLH = (0.25 ns/pF) CL + 112.5 ns tPLH = (0.20 ns/pF) CL + 80 ns tPHL = (1.3 ns/pF) CL + 248 ns tPHL = (0.45 ns/pF) CL + 102.5 ns tPHL = (0.35 ns/pF) CL + 72.5 ns Setup Time tTHL 5.0 10 15 tTHL 5.0 10 15 tPLH 5.0 10 15 tPHL 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 100 40 30 60 40 30 520 220 130 640 250 175 720 290 200 600 200 150 485 200 160 313 125 90 313 125 90 -- -- -- -- -- -- 260 110 65 1280 500 350 1440 580 400 750 300 220 970 400 320 625 250 180 625 250 180 -- -- -- -- -- -- -- -- -- ns ns ns -- -- -- 270 135 110 540 270 220 ns -- -- -- 125 75 65 250 150 130 ns -- -- -- 480 240 190 960 480 380 ns All Types Typ 40 30 25 Min -- -- -- Max 80 60 50 ns Unit ns Output Rise Time -- Segment Outputs tPLH ns tPHL tPLH ns tPHL tsu ns Hold Time th ns Latch Enable Pulse Width tWL(LE) ns * The formulas given are for the typical characteristics only.
MOTOROLA CMOS LOGIC DATA
MC14513B 379
20 ns INPUT C tPLH OUTPUT g 90% 50% 10% tPHL
20 ns VDD VSS VOH VOL
tTLH
tTHL
a. Data Propagation Delay: Inputs RBI, D and LE low, and Inputs A, B, BI and LT high.
20 ns INPUT C tPLH OUTPUT RBO tTLH 50% 10% tTHL 90% 50% 10% tPHL 90%
20 ns VDD VSS VOH VOL
b. Inputs A, B, D and LE low, and Inputs RBI, BI and LT high.
20 ns LE 10% th tsu INPUT C 50% VSS VOH OUTPUT g VOL 90% 50% VDD VSS VDD
c. Setup and Hold Times: Input RBI and D low, Inputs A, B, BI and LT high.
20 ns 90% 50% LE tWL(LE) 10%
20 ns VDD VSS
d. Pulse Width: Data DCBA strobed into latches. Figure 2. Dynamic Signal Waveforms
MC14513B 380
MOTOROLA CMOS LOGIC DATA
CONNECTIONS TO VARIOUS DISPLAY READOUTS
LIGHT EMITTING DIODE (LED) READOUT
VDD VDD
COMMON CATHODE LED
COMMON ANODE LED 1.7 V
1.7 V
VSS
VSS
INCANDESCENT READOUT
VDD VDD
FLUORESCENT READOUT
VDD
** DIRECT (LOW BRIGHTNESS)
FILAMENT (SUPPLY) VSS VSS VSS OR APPROPRIATE VOLTAGE BELOW VSS.
GAS DISCHARGE READOUT
APPROPRIATE VOLTAGE
LIQUID CRYSTAL (LC) READOUT
EXCITATION (SQUARE WAVE, VSS TO VDD)
VDD
VDD
1/4 OF MC14070B
VSS ** A filament pre-warm resistor is recommended to reduce filament thermal shock and increase the effective cold resistance of the filament.
VSS Direct dc drive of LC's not recommended for life of LC readouts.
MOTOROLA CMOS LOGIC DATA
MC14513B 381
LOGIC DIAGRAM
BI 4 15 a A7 14 b 13 c B1 12 d 11 e
17 f C2 16 g LT 30 D6 RBI 8 10 RBO
LE 5
TYPICAL APPLICATIONS FOR RIPPLE BLANKING
LEADING EDGE ZERO SUPPRESSION
DISPLAYS
CONNECT TO
a -- - -- g RBO 1 BA
a-- - -- g RBI DC RBO B A 1
a-- - -- g RBI DC RBO B A 0
a-- - -- g RBI DC B RBO A 0
a-- - -- g RBI DC B RBO A 0
a-- - - -g RBI DC B RBO A 0
RBI VDD (1) D C
MC14513B INPUT CODE 0 0 (0) 0 0 0
MC14513B 0 (0) 0 0 0
MC14513B 1 (5) 0 1 0
MC14513B 0 (0) 0 0 0
MC14513B 0 (1) 0 1 0
MC14513B 0 (3) 1 1
MC14513B 382
MOTOROLA CMOS LOGIC DATA
TYPICAL APPLICATIONS FOR RIPPLE BLANKING (Cont)
TRAILING EDGE ZERO SUPPRESSION
DISPLAYS
0
a-- - -- g RBO DC RBI BA 0
a -- - -- g RBO DC RBI B A 0
a -- - --g RBO DC RBI B A 0
a-- - -- g RBO DC RBI B A 1
a -- - --g RBO DC B RBI A 1
a -- - --g RBO DC B RBI A
CONNECT TO VDD (1)
MC14513B 0 1 (5) 0 1 0
MC14513B 0 (0) 0 0 0
MC14513B 0 (1) 0 1 0
MC14513B 0 (3) 1 1 0
MC14513B 0 (0) 0 0 0
MC14513B 0 (0) 0 0 INPUT CODE
MOTOROLA CMOS LOGIC DATA
MC14513B 383
OUTLINE DIMENSIONS
L SUFFIX CERAMIC DIP PACKAGE CASE 726-04 ISSUE G
-A-
18 10 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F FOR FULL LEADS. HALF LEADS OPTIONAL AT LEAD POSITIONS 1, 9, 10, AND 18. DIM A B C D F G J K L M N S INCHES MIN MAX 0.880 0.910 0.240 0.295 --- 0.200 0.015 0.021 0.055 0.070 0.100 BSC 0.008 0.012 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 22.35 23.11 6.10 7.49 --- 5.08 0.38 0.53 1.40 1.78 2.54 BSC 0.20 0.30 3.18 4.32 7.62 BSC 0_ 15_ 0.51 1.02
-B-
1 9 OPTIONAL LEAD CONFIGURATION (1, 9, 10, 18)
L C N -T-
SEATING PLANE
K F G D 18 PL 0.25 (0.010) J
M 18 PL M
M
TA
S
0.25 (0.010)
TB
P SUFFIX PLASTIC DIP PACKAGE CASE 707-02 ISSUE C
18 1 10
B
9
NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. MILLIMETERS MIN MAX 22.22 23.24 6.10 6.60 3.56 4.57 0.36 0.56 1.27 1.78 2.54 BSC 1.02 1.52 0.20 0.30 2.92 3.43 7.62 BSC 0_ 15_ 0.51 1.02 INCHES MIN MAX 0.875 0.915 0.240 0.260 0.140 0.180 0.014 0.022 0.050 0.070 0.100 BSC 0.040 0.060 0.008 0.012 0.115 0.135 0.300 BSC 0_ 15 _ 0.020 0.040
A C L
DIM A B C D F G H J K L M N
N F H G D
SEATING PLANE
K M J
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MC14513B 384
*MC14513B/D*
MOTOROLA CMOS LOGIC DATA MC14513B/D

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